1. Field of the Invention
The present invention relates to a method of correcting a design pattern for an integrated circuit and apparatus for performing the same. More particularly, the present invention relates to a method of correcting a design pattern in which different process defects that are independent from one another are optimally minimized, and an apparatus for performing the same.
2. Description of the Related Art
In general, an integrated circuit device, such as a semiconductor device, is manufactured by a circuit design process for designing a transcription circuit pattern and a fabrication process for forming the integrated circuit on a semiconductor substrate in accordance with the transcription circuit pattern. For example, an electric circuit pattern, which is to be formed in a semiconductor device, is formed on a mask film in the circuit design process, and the circuit pattern on the mask film is formed on the substrate such as a wafer through various unit fabrication processes. Hereinafter, the electric circuit pattern which is to be transcribed onto the mask film will be referred to as a design pattern.
The design pattern is a theory-oriented and virtual circuit pattern for realizing some desired electric characteristics of an integrated circuit from a theoretical point of view. In contrast, a practical pattern on the wafer is a process-oriented and actual circuit pattern that is transcribed from the design pattern by various unit processes and processing techniques. Accordingly, the practical pattern is necessarily different from the design pattern, which is a mother pattern of the practical pattern in a transcription process. This difference is known as a process error. In practice, when the process error is allowable in a manufacturing process, the practical pattern is determined to be a non-defective pattern and when the process error is not allowable, the practical pattern is determined to be a defective pattern. The process error that is allowable in a manufacturing process is known as an allowable error, and the allowable error or an allowable error range is usually considered in the circuit design process.
As the degrees of integration of recent semiconductor integrated circuits have been increasing, the design rules, contact areas, critical dimensions, etc. of semiconductor devices have been continuously decreasing. As a result, incidents of process failures and poor operation of the semiconductor devices have been increasing, thereby reducing product yields of the semiconductor devices. Thus, research is being conducted so that the process failures are reflected in the circuit design pattern, to thereby increase the product yields of the semiconductor devices. A layout of the design pattern is usually modified and corrected in view of the process failures, and the concept including a series of processes for the modifications and corrections based on the process failures is widely known as “Design for Manufacturability (DFM).”
According to the DFM process, typical process defects causing the above process failures or the poor operation of the semiconductor devices are detected and are classified into groups in accordance with the process failures, and the circuit design process is performed in such a manner that the process defects are minimized in a manufacturing process to thereby minimize the process failures in a semiconductor device. For example, the DFM process usually includes the modification of the layout of the design pattern so as to minimize the process defects.
In general, the process defects detected in a manufacturing process for a semiconductor device are classified into three categories: random defects, systematic defects and parametric defects. The random defect is randomly generated during a manufacturing process due to surrounding conditions such as specific process conditions. The systematic defect is caused by an insufficient transcription of the layout of the design pattern onto a wafer. The parametric defect includes a kind of defect that is caused by the insufficient transcription of the layout to the wafer and that leads to poor operation of the semiconductor device but not process failures.
The random defect is an unexpected defect generated in each of unit processes of the manufacturing process for the semiconductor device, and exemplarily includes a particle, a void that is randomly generated in the unit process and electrical/physical defects due to the particle and/or the void. In contrast, the systematic defect is caused by inconsistency between the design pattern and the practical pattern, and thus is decisively influenced by average process accuracy or the size of the allowable error or the allowable error range of the process. For example, when the practical pattern is formed on the wafer with reduced critical dimensions (CD), in a process system of which the structural characteristics are the same as those of the system for the pattern having non-reduced CDs, the printability of the design pattern to the wafer may be degraded, and there is much more chance of the process failures occurring due to the degraded printability. As the degrees of integration of semiconductor devices increase, each unit process is required to be performed more accurately, thereby increasing possibility of systematic defects. The parametric defect is not detected as a process defect by an inspection process. However, the parametric defect has a decisive effect on the poor operation of a semiconductor device, to thereby cause the reduction of product yield of the device. The random and the systematic defects directly cause process failures and finally lead to a breakdown of the semiconductor device due to the processing defects. In contrast, the parametric defect does not cause process failures but degrades the performance of the semiconductor device as if the process failures are generated in the semiconductor device. For that reason, the random and the systematic defects may be classified as catastrophic defects, and the parametric defect may be classified as a performance defect. The above process defects are independent from one another and have individual effects on the process failures of the semiconductor device.
According to a conventional DFM process, a process engineer determines a critical parameter, which is a physical quantity of the practical pattern for minimizing the process failures, with respect to each type of the defects, respectively, by analyzing the practical patterns or using engineering intuition based on personal experience. Then, a design engineer makes a synthetic judgment based on all of the different kinds of process failures caused by each type of the defects and integrates the defects into a single kind of a conceptual process failure. The single kind of conceptual process failure by the design engineer is referred to as a general failure. Thereafter, the design engineer determines a conceptual parameter that decisively causes the general failure and a correction value of the conceptual parameter, which is a critical quantity for minimizing the general failures, using a design tool or personal experience. Finally, the design engineer modifies the layout of the design pattern, which is a mother pattern of the practical pattern, based on the correction value.
There may be difficulties in automating layout modification of the design pattern. Since the types of process defects are independent from one another and have individual effects on the process failures, an individual modification of the design pattern for minimizing process failures caused by each type of defect may be easily automated. However, a modification of the design pattern for minimizing the general failures may be difficult to automate because each type of defect is independent from the others, and no common process parameter is found between each type of defect.
When a skilled process engineer gives some information on correction specifications and correction locations of a sample cell on a wafer to which a particular unit process has been performed, a design engineer extends the correction information to overall cells of the wafer, so that the design pattern that is to be transcribed onto the entire surface of the wafer is modified based on the correction marks and correction locations corresponding to the sample cell. Accordingly, when the modified layout of the design pattern is transcribed onto a wafer, the process defects detected by the process engineer are sufficiently prevented at all cells of the wafer, to thereby remarkably increase the product yield of the semiconductor device. For example, the skilled process engineer may give some information on correction specifications and correction locations of a sample cell on a wafer in view of an overlap margin between a contact and an active region, an overlap margin between a bit line and a contact, or a correction margin for optical proximity. Particularly, the process engineer prepares a manual including specifications on each defect, the correction locations and correction order among the locations, and gives the manual to the design engineer. The random defect, the systematic defect and the parametric defect are individually analyzed by the process engineer, and the correction specifications and locations of each defect are independently applied to the modification of the layout of the design pattern.
Recently, various DFM tools are used for analyzing the defects in sample cells due to various sizes and kinds of the sample cells and a large number of defects in the sample cell. Particularly, some of the DFM tools can automatically give some information on yield increase before and after modification of the layout of the design pattern as well as information on correction locations and the corrected defect, to thereby improve the efficiency and accuracy of the DFM process. For example, a critical area analysis (CAA) device has been widely used as the DFM tool for analyzing a critical area for detecting the random defect. In addition, a critical feature analysis (CFA) device has been widely used as the DFM tool for analyzing critical features of a specific processing characteristic that usually causes a systematic defect. The printability of a layout of the design pattern may be visually shown using a litho-friendly design (LFD) device, and thus the LFD device has been widely used as the DFM tool for the parametric defect. The above DFM tools may automatically provide the correction specifications and the correction locations in accordance with each type of defect.
However, there are many difficulties in identifying correlations between the types of defects, because each type of defect has different properties. For example, physical dimensions of the catastrophic defect are different from those of the performance defect. Accordingly, each of the above DFM tools automatically gives a characteristic function of each type of defect, respectively, and the skilled process engineer provides correction specifications and locations of the sample cell in accordance with each type of defect. Then, the skilled design engineer manually modifies the layout of the design pattern with respect to a library cell based on the characteristic functions and the correction specifications and locations of the sample cell.
FIG. 1 is a graph illustrating a characteristic function of each type of defect generated by a conventional DFM tool. In FIG. 1, Curve I is a random defect characteristic function generated by the CAA device, and Curve II is a parametric defect characteristic function generated by the LFD device. In addition, the horizontal axis indicates a process parameter for generating the processing defect, and the vertical axis indicates a physical quantity of the processing defects.
For example, when the modification of the layout of the design pattern is directed to optimizing gap distances within circuit patterns or an allowable processing error, the process parameter may include a gap distance between specific structures of the design pattern or a distance from a specific pattern. The gap distance between specific structures of the design pattern may function as a process parameter for both the random defect characteristic function and the parametric defect characteristic function, so that the horizontal axis in FIG. 1 indicates a gap distance of the design pattern.
The random defect is expressed as a relative size of the defects with respect to the entire cell size, and the parameter defect is expressed as a specific physical quantity indicating a performance decrease of a semiconductor device, so that the random defect is expressed as a percentage indicating a defect ratio, and the parametric defect is expressed as a specific physical dimension, such as a current intensity, a voltage, a sheet resistance or a capacitance. The vertical axis in FIG. 1 may indicate the defect ratio or the specific physical quantity. Curve I and Curve II are interpreted by the skilled process engineer, and the interpretation results are provided to the design engineer. The design engineer modifies the layout of the design pattern based on the interpretation results and personal experience, and generates an optimal layout of the design pattern for optimally minimizing the random and parametric defects simultaneously. If a normalizing parameter between the two independent defects of the percentage of defects and the physical quantity, such as a voltage, current, etc., is not suggested in the modification process by the design engineer, the modification process for minimizing both of the independent defects simultaneously necessarily depends on the personal experience of the design engineer. That is, the modification process to the design pattern may be difficult to automate due to personal factors in the modification process. Until now, the layout modification to the design pattern for the library cell in the wafer has been performed based on the interpretation results and the personal experience of the design engineer.
However, the conventional manual DFM process has problems of inconsistency and omission of the corrections due to the personal factors of the DFM process. In addition, when the modified layout of the design pattern is provided back to the process engineer for review in view of processing technologies (DFM review), there have been no common criteria for checking the modification between the process and design engineers, so that the DFM review by the process engineer is also dependent on the personal experience of the process engineer.
Accordingly, there is still a need for an automated DFM process for increasing correction consistency and reducing modification time when the design pattern needs to be corrected for optimally minimizing at least two independent defects simultaneously.